View LTC3901_275855.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Final Electrical Specifications
LTC3901 Secondary Side Synchronous Driver for Push-Pull and Full-Bridge Converters
FEATURES
s s s s
DESCRIPTIO
November 2003
s s s s
N-Channel Synchronous MOSFET Driver Programmable Timeout Reverse Inductor Current Sense Gate Drive Transformer Synchronization Sequence Monitor Wide VCC Supply Range: 4.5V to 11V 15ns Rise/Fall Times at VCC = 5V, CL = 4700pF Undervoltage Lockout Small SSOP-16 Package
The LTC(R)3901 is a secondary side synchronous rectifier driver designed to be used in isolated push-pull and fullbridge converter power supplies. The chip drives two external N-channel MOSFETs and accepts a transformer generated bipolar input to maintain sychronization with the primary side controller. The LTC3901 provides a full range of protection features for the external MOSFETs. A programmable timeout function is included that disables both drivers when the synchronization signal is missing or incorrect. Additionally, the chip senses the output inductor current through the drain-source resistance of the two MOSFETs, turning off the MOSFETs if the inductor current reverses. The LTC3901 also shuts off the drivers if the supply is low or if the synchronization sequence is incorrect.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s s
48V Input Isolated DC/DC Converters Isolated Telecom Power Supplies Distributed Power Step-Down Converters Industrial Control System Power Supplies Automotive and Heavy Equipment
TYPICAL APPLICATIO
ISOLATION BARRIER D3 T1 VIN 36V TO 72V RCSE2 RCSE1 MA MB ME RCSE3 DRVA DRVB LTC3723 PUSH-PULL CONTROLLER COMP VFB SDRA SDRB C SYNC RCSF2 MF RCSF1
CZ
CSE + ME CSE - CSF + MF CSF -
VCC CVCC RVCC
GND LTC3901 PVCC CPVCC RTMR
PGND TIMER
RCSF3 SYNC T2 RK OUT FB CFB OPTOCOUPLER DRIVER CK COMP
RSYNC RF CF
RE
Figure 1. Simplified Isolated Push-Pull Converter
3901i
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
L1 RZ COUT
U
U
+
VOUT 12V
RB QREG
DZ
CTMR
R1
RC CC
3901 F01
R2
1
LTC3901
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW PVCC 1 ME 2 ME 3 PGND 4 CSE - 5 CSE+ 6 TIMER 7 GND 8 16 VCC 15 MF 14 MF 13 PGND 12 CSF - 11 CSF + 10 GND 9 SYNC
Supply Voltage VCC, PVCC ............................................................................ 12V Input Voltage CSE-, CSF-, TIMER ................. -0.3V to (VCC + 0.3V) SYNC ...................................................... -12V to 12V Input Current CSE+, CSF+ ..................................................................... 15mA Operating Temperature Range (Note 2) ...-40C to 85C Storage Temperature Range ..................-65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC3901EGN
GN PART MARKING 3901
GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 150C, JA = 130C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes specifications which apply over the full operating temperature range. VCC = 5V, TA = 25C unless otherwise specified. (Note 3)
SYMBOL VCC VUVLO IVCC Timer VTMR ITMR tTMRDIS VTMRMAX ICS+ ICS- VCSMAX VCS SYNC Input ISYNC VSYNCP VSYNCN Driver Output RONH RONL IPK Driver Pull-Up Resistance Driver Pull-Down Resistance Driver Peak Output Current IOUT = -100mA
q
ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Range VCC Undervoltage Lockout Threshold VCC Undervoltage Lockout Hysteresis VCC Supply Current
CONDITIONS
q
MIN 4.5
q q q
TYP 5 4.1 0.5 0.5 7
MAX 11 4.5 1 15 10% -10 120
UNITS V V V mA mA V A ns V
Rising Edge Rising Edge to Falling Edge VSYNC = 0V fSYNC = 100kHz, CME = CMF = 4700pF (Note 4)
Timer Threshold Voltage Timer Input Current Timer Discharge Time Timer Pin Clamp Voltage CS+ Input Current CS- CS+ Input Current Pin Clamp Voltage VTMR = 0V CTMR = 1000pF, RTMR = 4.7k CTMR = 1000pF, RTMR = 4.7k VCS+ = 0V VCS - = 0V IIN = 5mA, Driver Off VCS - = 0V (Note 7) VSYNC = 10V (Note 5)
q q q
-10%
VCC/5 -6 40 2.5
Current Sense (Note 6)
q q
1 1 11 7.5 3 10.5 13.5 18 10 1.8 -1.0
Current Sense Threshold Voltage
q
SYNC Input Current SYNC Input Positive Threshold SYNC Positive Input Hysteresis SYNC Input Negative Threshold SYNC Negative Input Hysteresis
q q q
1 1.0 -1.8 1.4 0.2 -1.4 0.2 0.9 0.8
(Note 5)
1.2 1.6 1.2 1.6
IOUT = 100mA
q
(Note 5)
2
2
U
A A V mV mV A V V V V A
3901i
W
U
U
WW
W
LTC3901
ELECTRICAL CHARACTERISTICS
SYMBOL td t r, t f PARAMETER SYNC Input to Driver Output Delay Driver Rise/Fall Time Switching Characteristics (Note 8)
The q denotes specifications which apply over the full operating temperature range. VCC = 5V, TA = 25C unless otherwise specified. (Note 3)
CONDITIONS CME = CMF = 4700pF, VSYNC = 5V CME = CMF = 4700pF, VSYNC = 5V
q
MIN
TYP 60 15
MAX 120
UNITS ns ns
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3901E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design; characterization and correlation with statisitical process controls. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 4: Supply current in normal operation is dominated by the current needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage, switching frequency and the external MOSFETs used. Note 5: Guaranteed by design, not subject to test. Note 6: Both CSE+, CSE- and CSF+, CSF- current sense comparators have the same performance specifications. Note 7: The current sense comparator threshold has a 0.33%/C temperature coefficient (TC) to match the TC of the external MOSFET RDSON. Note 8: Rise and fall times are measured using 10% and 90% levels. Delay times are measured from 1.4V at SYNC input to 20%/80% levels at the driver output.
TYPICAL PERFOR A CE CHARACTERISTICS
Timeout vs VCC
5.25 5.20 5.15 5.10 TA = 25C RTMR = 51k CTMR = 470pF 5.25 5.20 5.15 5.10 VCC = 5V RTMR = 51k CTMR = 470pF
TIMEOUT (s)
TIMEOUT (s)
5.05 5.00 4.95 4.90 4.85 4.80 4.75 4 5 6 8 7 VCC (V) 9 10 11
5.05 5.00 4.95 4.90 4.85 4.80 4.75 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
TIMEOUT (s)
Current Sense Threshold vs Temperature
18 17 VCC = 5V, 11V 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 25 50 75 -50 -25 TEMPERATURE (C) 18 17
CURRENT SENSE THRESHOLD (mV)
16 15 14 13 12 11
SYNC POSITIVE THRESHOLD (V)
VCS(MAX) CLAMP VOLTAGE (V)
UW
3901 G01
Timeout vs Temperature
10
Timeout vs RTMR
TA = 25C 9 VCC = 5V = 470pF C 8 TMR 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 RTMR (k)
3901 G03
3901 G02
VCS(MAX) Input Current
TA = 25C
Clamp Voltage vs CS+
1.8 1.7 1.6 1.5 1.4
SYNC Positive Threshold vs Temperature
VCC = 11V VCC = 5V
1.3 1.2 1.1
100
125
10
0
5
25 10 15 20 CS+ INPUT CURRENT (mA)
30
3901 G05
1.0 -50 -25
0
25
50
75
100
125
TEMPERATURE (C)
3901 G06
3901 G04
3901i
3
LTC3901 TYPICAL PERFOR A CE CHARACTERISTICS
SYNC Negative Threshold vs Temperature
-1.0 VCC = 5V, 11V
SYNC NEGATIVE THRESHOLD (V)
-1.1
PROPAGATION DELAY (s)
-1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -50 -25 0 25 50 75 100 125
100 90 80 70 60 50 40 4 5 6 7 8 9 10 11 SYNC TO MF SYNC TO ME
PROPAGATION DELAY (s)
TEMPERATURE (C)
3901 G07
Propagation Delay vs CLOAD
120 110
PROPAGATION DELAY (s)
TA = 25C VCC = 5V
RISE/FALL TIME (ns)
100 90 80 70 60 50 40 1 2 3 4 6 7 CLOAD (nF) 5 8 9 10 SYNC TO ME SYNC TO MF
RISE/FALL TIME (ns)
Rise/Fall Time vs Load Capacitance
50 45 40
RISE/FALL TIME (ns) UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V)
TA = 25C VCC = 5V
VCC SUPPLY CURRENT (mA)
35 30 25 20 15 10 5 0 0 1 2 3 4 56 CLOAD (nF) 7 8 9 10 RISE TIME FALL TIME
4
UW
3901 G10 3901 G13
Propagation Delay vs VCC
120 110 TA = 25C CLOAD = 4.7nF 120 110 100 90 80 70 60 50
Propagation Delay vs Temperature
VCC = 5V CLOAD = 4.7nF
SYNC TO ME
SYNC TO MF
40 -50 -25
0
25
50
75
100
125
VCC (V)
3901 G08
TEMPERATURE (C)
3901 G09
Rise/Fall Time vs VCC
50 45 40 35 30 25 20 15 10 5 0 4 5 6 7 8 9 10 11 VCC (V)
3901 G11
Rise/Fall Time vs Temperature
50 45 40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 RISE TIME FALL TIME VCC = 5V CLOAD = 4.7nF
TA = 25C CLOAD = 4.7nF
RISE TIME FALL TIME
3901 G12
Undervoltage Lockout Threshold Voltage vs Temperature
4.5 4.4 4.3 4.2 RISING EDGE 4.1 4.0 3.9 3.8 3.7 3.6 3.5 FALLING EDGE 3.4 3.3 3.2 3.1 3.0 0 25 50 75 -50 -25 TEMPERATURE (C) 20 18 16 14 12 10 8 6 100 125
VCC Supply Current vs Temperature
CLOAD = 4.7nF
VCC = 11V
VCC = 5V
4 -50 -25
0
25
50
75
100
125
TEMPERATURE (C)
3901 G14 3901 G15
3901i
LTC3901 TYPICAL PERFOR A CE CHARACTERISTICS
VCC Supply Current vs Load Capacitance
30 TA = 25C 25 SUPPLY CURRENT (mA) VCC = 11V 20 15 10 VCC = 5V 5 0 0 1 2 3 4 56 CLOAD (nF) 7 8 9 10
PI FU CTIO S
PVCC (Pin 1): Driver Supply Input. This pin powers the ME and MF drivers. Bypass this pin to PGND using a 4.7F capacitor in close proximity to the LTC3901. This pin should be connected to the same supply voltage as the VCC pin. ME (Pin 2, 3): Driver Output for ME. This pin drives the gate of the external N-channel MOSFET, ME. PGND (Pin 4,13): Power Ground. Both drivers return to this pin. Connect PGND to a high current ground node in close proximity to the sources of ME and MF. CSE+, CSE- (Pin 6, 5): ME Current Sense Differential Input. Connect CSE+ through a series resistor to the drain of ME and CSE- through a series resistor to the source of ME. The LTC3901 monitors the CSE inputs 250ns after ME goes high. If the inductor current reverses and flows into ME causing CSE+ to rise above CSE- by more than 10.5mV, the LTC3901 pulls ME low. See the Current Sense section for more details on choosing the resistance values for RCSE1 to RCSE3. TIMER (Pin 7): Timer Input. Connect this pin to an external R-C network to program the timeout period. The LTC3901 resets the timer at every positive and negative transition of the SYNC input. If the SYNC signal is missing or incorrect, the LTC3901 pulls both ME and MF low once the TIMER pin goes above the timeout threshold. See the Timer section for more details on programming the timeout period. GND (Pin 8,10): Signal Ground. All internal low power circuitry returns to this pin. To minimize differential ground currents, connect GND to PGND right at the LTC3901. SYNC (Pin 9): Driver Synchronization Input. 0V at this pin forces both ME and MF high after an inital negative pulse. A subsequent positive pulse at SYNC input forces ME to pull low, whereas a negative pulse forces MF to pull low. The SYNC signal should alternate between positive and negative pulses. If the SYNC signal is incorrect, the LTC3901 pulls both MF and ME low. CSF+, CSF - (Pin 11, 12): MF Current Sense Differential Input. Connect CSF+ through a series resistor to the drain of MF and CSF- through a series resistor to the source of MF. The LTC3901 monitors the CSF inputs 250ns after MF goes high. If the inductor current reverses and flows into MF causing CSF+ to rise above CSF- by more than 10.5mV, the LTC3901 pulls MF low. See the Current Sense section for more details on choosing the resistance values for RCSF1 to RCSF3. MF (Pin 14, 15): Driver Output for MF. This pin drives the gate of the external N-channel MOSFET, MF. VCC (Pin 16): Power Supply Input. All internal circuits except the drivers are powered from this pin. Bypass this pin to GND using a 1F capacitor in close proximity to the LTC3901.
3901i
UW
3901 G16
U
U
U
5
LTC3901
BLOCK DIAGRA
APPLICATIO S I FOR ATIO
Overview
Push-pull and full bridge converters use power transformers to provide input to output isolation and voltage stepup/down. Diodes are used as a simple solution for secondary side rectification. Unfortunately, as output currents increase, the loss associated with diode forward voltage drop results in low overall efficiency. The LTC3901 overcomes this problem by providing control and drive for two external N-channel synchronous MOSFETs. Synchronization to the primary side controller is maintained through a small signal transformer. Figure 1 shows a simplified push-pull converter application. T1 is the power transformer; MA and MB are the primary side power transistors driven by the LTC3723 controller's DRVA and DRVB outputs. The gate drive transformer T2 is driven by the LTC3723's SDRA and SDRB outputs and provides the synchronization signal to the LTC3901 on the secondary side. When both SDRA and SDRB are high, there is no voltage across the transformer's primary and the LTC3901 SYNC input is approximately 0V. According to the polarity of the transformer: if SDRA goes low while SDRB is high, SYNC is positive; if SDRB goes low while SDRA is high, SYNC is negative. ME and MF are the secondary side synchronous switches driven by the LTC3901's ME and MF output. Inductor L1 and capacitor
6
U
W
W
SYNC 9 +1.4V -1.4V CSE+ 6 10.5mV CSE- 5 CSF+ 11 10.5mV CSF- 12 S- SYNC - SYNC AND DRIVER LOGIC DISABLE DRIVER UVLO TIMER RESET S+ SYNC+ 16 VCC 1 PVCC 3 4 ME PGND ISE ZCSE 11V
-+
14 MF 13 PGND
-+
ZCSF 11V
ISF
TMR TIMER 7 R1 180k R2 45k
ZTMR 0.5 * VCC MTMR
8 10 GND GND
3901 BD
U
U
COUT form the output filter, providing DC output voltage to the load. The feedback path from VOUT through the optocoupler driver and optocoupler back to the primary side controller is also shown in Figure 1. Each full cycle of the push-pull converter consists of four distinct periods. Figure 2 shows the push-pull converter waveforms. In the first period, SDRA goes low (followed by DRVA going high) and T2 generates a positive voltage at the LTC3901's SYNC input. The LTC3901's ME output then pulls low. Current flows to the load through MOSFET MF, T1's secondary and L1.
DRA
DRB SDRA
SDRB
SYNC
0V
ME MF
3901 F02
Figure 2. Push-Pull Converter Switching Waveforms
3901i
LTC3901
APPLICATIO S I FOR ATIO
In the second period, SDRA goes high and T2 provides approximately 0V at the LTC3901 SYNC input. This causes the LTC3901's ME output to go high and both MOSFET ME and MF to conduct. This is the free-wheeling period with T1 secondary winding shorted. In the third period, SDRB goes low (followed by DRVB going high) and T2 generates a negative voltage at the LTC3901's SYNC input. The LTC3901's MF output then pulls low. Current flows to the load through MOSFET ME, T1's secondary and L1. The last period is also a free-wheeling period like the second period. Both SDRA and SDRB are high and the LTC3901 forces both MOSFETs ME and MF to conduct. External MOSFET Protection A programmable timer and two differential input current sense comparators are included in the LTC3901 for protection of the external MOSFETs during power down and Burst Mode(R) operation. The chip also shuts off the MOSFETs if VCC < 4.1V or if the synchronization sequence is incorrect. When the primary controller is powering down, the LTC3901 continues to operate for a while by drawing power from the VCC bypass cap, CVCC. The primary controller synchronous output stops switching and the LTC3901 SYNC input goes to 0V. Both ME and MF remain on and the decreasing inductor current continues to flow into the load. Once the inductor current decreases to zero, it reverses direction, discharging the output capacitor COUT to GND through both MOSFETs. At the same time, the CVCC voltage continues to drop. When the voltage drops below 4.1V, the LTC3901 shuts down and pulls both ME and MF low. This causes the inductor current to stop suddenly and the drain voltage of both MOSFETs to fly high, due to the buildup of inductor energy. If the inductor energy is high due to a long period of current reversal, the drain voltage can go above the MOSFET's voltage rating and cause damage to the MOSFET. MOSFETs are also kept on for long periods when the primary controller enters Burst Mode operation. Both ME and MF stop switching until the primary controller exits Burst Mode operation. This may also cause the inductor current to reverse and the drains to fly high.
Burst Mode is a registered trademark of Linear Technology Corporation.
U
In these situations, the timer and/or current sense comparator shuts off the drivers before or immediately after the inductor current reverses direction. This prevents the buildup of inductor energy. Timer The timer circuit (Figure 3) operates by using an external R-C charging network to program the timeout period. On every transition at the SYNC input, the chip generates a 200ns pulse to reset the timer capacitor. If the SYNC signal is missing or incorrect (allowing the timer capacitor voltage to go high) it shuts off both drivers once the voltage reaches the timeout threshold. Figure 4 shows the timer waveforms. The timeout period is determined predominantly by the external RTMR and CTMR values and is independent of the VCC voltage. This independence is achieved by making the timeout threshold a ratio of VCC. The ratio is 0.2x, set internally by R1 and R2 (see Figure 3). The Timeout period should be programmed to around 1 period of the primary switching frequency using the following formula: TIMEOUT = 0.2 * RTMR * CTMR + 0.27E-06
VCC 16 LTC3901 TMR TIMEOUT VCC TIMER ZTMR 0.5 * VCC 7 CTMR 470pF RTMR 32k R1 180k R2 45k TIMER RESET MTMR
3901 F03
W
UU
Figure 3. Timer Circuit
SYNC 0V
ME MF TIMER RESET (INTERNAL)
TIMER
TIMEOUT THRESHOLD
3901 F02
Figure 4. Timer Waveforms
3901i
7
LTC3901
APPLICATIO S I FOR ATIO
To reduce error in the timeout setting due to the discharge time, select CTMR between 100pF and 1000pF. Start with a CTMR around 470pF and then calculate the required RTMR. CTMR should be placed as close as possible to the LTC3901 with minimum PCB trace between CTMR, the TIMER pin and GND. This is to reduce any ringing caused by the PCB trace inductance when CTMR discharges. This ringing may introduce error to the timeout setting. The timer input also includes a current sinking clamp circuit (ZTMR in Figure 3) that clamps this pin to about 0.5 * VCC if there is missing SYNC/timer reset pulse. This clamp circuit prevents the timer capacitor from getting fully charged up to the rail, which would result in a longer discharge time. The current sinking capability of the circuit is around 1mA. The timeout function can be disabled by connecting the timer pin to GND. Synchronization Sequence A typical push-pull converter cycle always turns off ME and MF alternately. The SYNC input should alternate between a positive and negative pulse. The LTC3901 includes a sequential logic to monitor the SYNC input pulses. If after one positive pulse the SYNC comparator receives another positive pulse, the LTC3901 sequential logic shuts off both drivers until a negative pulse appears. The same applies to double negative pulses; the driver will turn on only after receiving a positve pulse. This is to protect the external components in situations where only one polarity of the SYNC pulse is present and the corresponding driver remains on. Figure 5 shows the SYNC double pulse operation. The LTC3901 has two separate SYNC comparators (S+ and S- in the Block Diagram) to detect the positive and negative pulses. The threshold voltages of both comparators are designed to be of the same magnitude but opposite in polarity. In some situations, for example during power-up or power-down, the SYNC pulse magnitude may be low (slightly higher or lower than the threshold of the comparators). This can cause only one of the SYNC comparators to trip. This also appears as a double pulse to the sequential logic and both drivers will be shut off. Current Sense The differential input current sense comparators are used for sensing the voltage across the drain-to-source termi-
8
U
SECOND NEGATIVE SYNC PULSE, BOTH ME AND MF PULL LOW SYNC 0V ME MF EXPECTED POSITIVE SYNC PULSE, MF PULLS HIGH
3901 F05
W
U
U
Figure 5. SYNC Double Pulse Operation
nal of the MOSFET through the CSX+ and CSX- pins. There are two sets of comparator inputs, one for each MOSFET (ME and MF). If the inductor current reverses into the MOSFET causing CSX+ to rise above CSX- by more than 10.5mV, the LTC3901 turns off the respective MOSFET. This comparator is used to prevent inductor reverse current buildup during power-down or Burst Mode operation, which may cause damage to the MOSFETs. The 10.5mV input threshold has a positive temperature coefficient, which closely matches the TC of the external MOSFET RDS(ON). The current sense comparator is only active 250ns after the respective driver output goes high; this is to avoid any ringing immediately after the MOSFETs are switched on. Under no/light load conditions, if the inductor average current is less than half of its peak-to-peak ripple current, the inductor current will reverse into MOSFETs during a portion of the free-wheeling period, forcing CSX+ to rise above CSX-. The current sense comparator input threshold is set at 10.5mV to prevent tripping under this normal no load condition. If at no load, the product of the inductor negative peak current and MOSFET RDS(ON) is higher than 10.5mV; this may trip the comparator and force the LTC3901 to operate in discontinuous mode. Figure 6 shows the LTC3901 operating in discontinuous mode; the driver's output goes low before the next SYNC transition edge when the inductor current goes negative. In pushpull topology, both MOSFETs conduct the same amount of current during the free-wheeling period; this will trip both comparators at the same time. Discontinuous mode is sometimes undesirable because if the load current suddenly increases when the MOSFETs are off, it creates a large output voltage drop. To overcome this, add a resistor divider, RCSX1 and RCSX2 at the CSX+ pin to increase the 10.5mV threshold so that the LTC3901 operates in continuous mode at no load.
3901i
LTC3901
APPLICATIO S I FOR ATIO
The LTC3901 CSX+ pin has an internal current sinking clamp circuit (ZCSX in the Block Diagram) that clamps the pin to around 11V. The clamp circuit, together with the external series resistor RCSX1, protects the CSX+ pins from the high MOSFET drain voltage in the power delivery cycle. During the power delivery cycle, one of the MOSFETs (ME or MF) is off. The drain voltage of the MOSFET that is off is determined by the primary input voltage and the transformer turn ratio. This voltage can be high and may damage the internal circuit if CSX+ is connected directly to the drain of its MOSFET. The current sinking capability of the clamp circuit is 5mA minimum. The value of the resistorsRCSX1, RCSX2 and RCSX3 should be calculated using the following formulas to meet both the clamp and threshold voltage requirements: k = {48 * IRIPPLE * RDS(ON)} -1 RCSX2 = {200 * VIN(MAX) * NS/NP -2200 * (1 + k)} /k RCSX1 = k * RCSX2 RCSX3 = {RCSX1 * RCSX2} / {RCSX1 + RCSX2} If k = 0 or less than zero, RCSX2 is not needed and RCSX1 = RCSX3 = {VIN(MAX) * (NS/NP) - 11V} / 5mA where: IRIPPLE = Inductor peak-to-peak ripple current RDS(ON) = On-resistance of MOSFET at IRIPPLE/2 VIN(MAX) = Primary side main supply maximum input voltage NS/NP = Power transformer T1, turn ratio If the LTC3901 still operates in discontinuous mode with the calculated resistance value, increase the value of RCSX1 to raise the threshold. The resistors RCSX1 and RCSX2 and the CSX+ pins input capacitance plus the PCB trace capacitance forms an R-C delay; this slows down the response time of the comparators. The resistors and CSX+ input leakage currents also create an input offset error. To minimize this delay and error, do not use resistance value higher than required and make the PCB trace from the resistors to the LTC3901 CSX+/CSX- pins as short as possible . Add a series resistor, RCSX3, with value equal to parallel sum of RCSX1 and RCSX2 to the CSX- pin and connect the other end of RCSX3 directly to the source of the MOSFET.
U
SYNC Input Figure 7 shows the external circuit for the LTC3901 SYNC input. The gate drive transformer (T2) should be selected based on the primary switching frequency and SDRA/ SDRB output voltage. The values of the CSG and RSYNC should then be adjusted to obtain a optimum SYNC pulse shape and amplitude. The amplitude of the SYNC pulse should be much higher than the LTC3901 SYNC threshold of 1.4V. Amplitudes greater than 5V will help to speed up the SYNC comparator and reduce the propagation delay from SYNC to the drivers. When SDRA and SDRB lines go low, the resulting undershoot or overshoot must not exceed the minimum SYNC threshold of 1V.
SDRA SDRB SYNC 0V ME MF L1 CURRENT CURRENT SENSE COMPARATOR TRIP 0V
W
U
U
Figure 6a. Discontinuous Mode Operation at No Load
SYNC 0V
ME MF L1 CURRENT ADJUSTED CURRENT SENSE THRESHOLD
0V
Figure 6b. Continuous Mode Operation with Adjusted Current Sense Threshold
CSG 0.1F SDRB PRIMARY CONTROLLER SDRA RSG 220
3901 F06
T2
LTC3901 SYNC RSYNC 4.7k
Figure 7. SYNC Input Circuit
3901i
9
LTC3901
APPLICATIO S I FOR ATIO
VCC/PVCC Regulator The VCC/PVCC supply for the LTC3901 can be generated by peak rectifying the transformer secondary winding as shown in Figure 8. The Zener diode DZ sets the output voltage (VZ to 0.7V). Resistor RB (on the order of a few hundred ohms), in series with the base of QREG, may be required to surpress high frequency oscillations depending on QREG's selection. A power MOSFET can also be used by increasing the zener diode value to offset the drop of the gate-to-source voltage. The VCC input is separated from the PVCC input through a 100 resistor. This lowers the driver switching feedthrough. Connect a 1F bypass capacitor for the VCC supply. PVCC supply current varies linearly with the supply voltage, driver load and clock frequency. A 4.7F bypass capacitor for the PVCC supply is sufficient for most applications. Alternatively, the LTC3901 can be powered directly by VOUT if the voltage is higher than 4.5V. This reduces the number of external components needed. The LTC3901 has an UVLO detector that pulls the drivers' output low if VCC < 4.1V. The output remains off from VCC = 1V to 4.1V. The UVLO detector has 0.5V of hysteresis to prevent chattering. In a typical push-pull converter, the secondary side circuits have no power until the primary side controller starts operating. Since power for the LTC3901 is derived from the power transformer T1, the LTC3901 will initially remain off. During this period (VCC < 4.1V), the synchronous MOSFETs ME and MF will remain off and the MOSFETs' body diodes will conduct. The MOSFETs may experience very high power dissipation due to a high voltage drop in the body diodes. To prevent MOSFET damage, a VCC voltage greater than 4.1V should be provided quickly. The VCC supply circuit in Figure 8 will provide power for the
T1 SECONDARY WINDING D3 MBR0540
0.1F
RZ 2k
RB OPTIONAL 6V DZ CPVCC 4.7F
QREG FZT690B PVCC VCC CVCC 1F
3901 F07
RVCC 100
Figure 8. VCC/PVCC Regulator
3901i
10
U
LTC3901 within the first few switching pulses of the primary controller, preventing overheating of the MOSFETs. Full-Bridge Converter Application The LTC3901 can be used in full-bridge converter applications. Figure 9 shows a simplified full-bridge converter circuit. The LTC3901 circuit and operation is the same as in the push-pull application (refer to Figure 1). On the primary side there are four power MOSFETs, MA to MD, driven by the respective outputs of the primary controller. Transformer T3 and T4 step up the gate drives for MA and MC. Each full cycle of the full-bridge converter includes four distinct periods which are similar to those found in the push-pull application. Figure 10 shows the full-bridge converter switching waveforms. The shaded areas correspond to power delivery periods. In the first period, MB turns off, E goes low (followed by MA turning on), and the LTC3901 forces ME to turn off. The primary side delivers power to the load through MOSFET MF, T1 and L1. In the second period, MA remains on, MD turns off, and MC turns on. E goes high and the LTC3901 forces both ME and MF to conduct. This is the free-wheeling period with the T1 secondary output shorted. In the third period, MA turns off, F goes low (followed by MB turning on), and the LTC3901 forces MF to turn off. The primary side delivers power to the load through MOSFET ME, T1 and L2. Like the second period, the last period is a free-wheeling period. MB remains on, MC turns off, MD turns on, F goes high, and the LTC3901 forces both ME and MF to conduct. The timeout and current sense operations are the same as in the push-pull application.
W
U
U
LTC3901
APPLICATIO S I FOR ATIO
VIN MA T3 T4
ISOLATION BARRIER MC L1 T1 COUT L2
MB MD D3 CZ RZ RB QREG RCSE2 RCSE1 ME RCSE3 the A B C D RCSF2 MF F CSYNC RCSF1 11 14 12 RCSF3 T2 RK OUT FB CFB RC CC
3901 F08
LTC3722-1 FULL-BRIDGE CONTROLLER COMP VFB E
RSYNC RF CF
RE
Figure 9. Simplified Isolated Full-Bridge Converter
MA MB
MC MD E F
SYNC
ME MF
3901 F09
Figure 10. Full-Bridge Converter Switching Waveforms
U
+
VOUT DZ 6 3 5 CSE + ME CSE - CSF + MF CSF - SYNC PGND TIMER 4,13 7 CTMR R1 GND LTC3901 PVCC 8,10 VCC 16 CVCC RVCC 1 CPVCC RTMR 9 OPTOCOUPLER DRIVER CK COMP R2
W
UU
MOSFET Selection The required MOSFET RDS(ON) should be determined based on allowable power dissipation and maximum required output current. The MOSFETs body diodes conduct during the power-up phase, when the LTC3901 VCC supply is ramping up. The ME and MF signals stay low and the inductor current flows through the body diodes. The body diodes must be able to handle the load current during start-up until VCC reaches 4.1V.
0V
The LTC3901 drivers dissipate power while the MOSFETs are switching. The power dissipation increases with switching frequency, PVCC, and size of the MOSFETs. To calculate the driver dissipation, the total gate charge QG is used. This parameter is found on the MOSFET manufacturers' data sheets. The power dissipated in each LTC3901 MOSFET driver is: PDRIVER = QG * PVCC * fSW where fSW is the switching frequency of the converter.
3901i
11
LTC3901
APPLICATIO S I FOR ATIO
PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3901: 1. Connect the 1F CVCC bypass capacitor as close as possible to the VCC and GND pins. Connect the 4.7F CPVCC bypass capacitor as close as possible to the PVCC and PGND pins. 2. Connect the two MOSFET drain terminals directly to the transformer. The two MOSFET sources should be as close together as possible.
PACKAGE DESCRIPTIO
.045 .005
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF
.254 MIN
.150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988)
.0165 .0015
.0250 TYP 1 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270)
RELATED PARTS
PART NUMBER DESCRIPTION LTC1693 LTC1698 LT1950 LTC3722 LTC3723 LTC3900 High Speed Single/Dual N-Channel MOSFET Drivers Isolated Secondary Synchronous Rectifier Controller Forward Controller Synchronous Dual Mode Phase Modulated Full-Bridge Controller Synchronous Push-Pull Controller Synchronous Rectifier Driver for Forward Converters Similar Function to LTC3901but for Forward Converter
3901i LT/TP 1103 1K * PRINTED IN USA
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
www.linear.com
U
3. Keep the timer, SYNC and VCC regulator circuit away from the high current path of ME, MF and T1. 4. Place the timer capacitor, CTMR as close as possible to the LTC3901. 5. Keep the PCB trace from the resistors RCSX1, RCSX2 and RCSX3 to the LTC3901 CSX+/CSX- pins as short as possible. Connect the other ends of the resistors directly to the drain and source of the MOSFET. 6. Make the connection between GND and PGND right at the LTC3901 pins.
.015 .004 x 45 (0.38 0.10) 0 - 8 TYP .053 - .068 (1.351 - 1.727) .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC
GN16 (SSOP) 0502
U
W
U
U
COMMENTS CMOS Compatible Input, VCC Range: 4.5V to 13.2V Use with the LT1681, Optocoupler Driver, Pulse Transformer Synchronization Programmable Volt-Second Clamp and Slope Compensation 50W to 2kW Power Supply Design, Adaptive Direct Sense ZVS
(c) LINEAR TECHNOLOGY CORPORATION 2003

▲Up To Search▲

Price & Availability of LTC3901

	To Download LTC3901 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .